Inferno C++ to Verilog 1.0
in Education \ Science
Convert C++ software programs into synthesisable Verilog using the Clang compiler frontend to parse and SystemC for intermediates. Inferno C++ to Verilog 1.0 License - BSD License
Experimental ESL Compiler from C to Verilog Central Silicon 1.0 License - GNU General Public License (GPL)
ACMgen is an automatic code generator of Asynchronous Communications Mechanisms based on the generation of Petri nets models that can be formally verified against some properties and then transformed into a real implementation (e.g. C++ or Verilog). ACM code generator 1.0 License - GNU General...
libLCS is a hardware description library in C++ aiming to be as powerfull and easy as the Verilog HDL. It currently supports logic gates, flipflops, clock, and facilitates delays, continuous assignments and variable value dumping into VCD files.
The Verilog Construction Toolkit is a C++ library which provides the ability to read in, create and or modify verilog cell-based structural netlists.
What would verilog code translated to unlambda look like? This question has puzzled me for a long time and I've decided to do a unlambda backend to my c->verilog compiler. Come to think of it, why stop at unlambda? I will go all the way to NAND gates. Scheme-C-Verilog-Unlambda-NAND-Gates...
Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
FpgaC compiles a subset of the C language to net lists which can be imported into an FPGA vendors tool chains. C provides an excellent alternative to VHDL/Verilog for algorithmic expression of FPGA reconfigurable computing tasks. More info in wiki.
RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.
Verilog2C++: A translater from Verilog to C++
Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine. V2000 Project 1.0 License - GNU Library or Lesser General Public License (LGPL)